Our unremitting pursuit of speed makes the pace of terminal product upgrading faster and faster. How to speed up product launch for future demand? How to deal with the challenges of high-speed interface design and testing? Recently, the 2021 high-speed interface joint test forum jointly held by global leaders in the test and measurement industry, Anritsu, Tektronix and GRL, invited leading manufacturers of chip design, IP and equipment to conduct in-depth discussions in response to industry hotspots.

As a cutting-edge high-speed interface IP enterprise, Xinyaohui Technology was invited to attend this event. Liu Haopeng, the technical support director of Xinyaohui Technology, gave a wonderful sharing on the theme of “Prospects for the Development of Consumer Electronics Interfaces – Will USB Dominate the World?”, and introduced Xinyaohui’s USB PHY IP solution in depth.

Picture: Liu Haopeng, Technical Support Director of Xinyaohui Technology

Development History丨30 years of development, the spirit of the USB king is gradually emerging

The full name of USB is Universal Serial Bus, and the name reflects its original intention of strong versatility, high transmission rate, good compatibility and plug-and-play. So far, the USB interface standard has gone through three stages. The first stage began in 1995. In order to solve the problem of interface versatility, the first-generation USB standard came out, with a transmission speed of only 1.5Mbps, and the industry’s response was mediocre. The second stage began in 2000, and the USB 2.0 transmission speed reached 480Mbps, which was widely used in various data transmission applications. But in the following 5 years, there is no new bright spot in the USB standard.

The new breakthrough is in the third stage, which is marked by the release of USB 3.0 in 2008 and the breakthrough of the transmission speed to 5Gbps. Subsequently, USB3.1 with a transmission speed of 10Gbps in 2013 and USB3.2 with a transmission speed of 20Gbps in 2017 were successively released. The latest USB4 released in 2019 has a maximum speed of 40Gbps, and terminal products will be launched at the end of 2020. In particular, Intel Core 11 products integrate Thunderbolt 4 supporting USB4, which is regarded by the industry as a landmark event for the popularization of the USB4 standard.

Figure: History of USB Standard Development

Future Trend丨USB Technology Evolution Aims at High Speed ​​and Compatibility

Over the years, the USB interface standard has been continuously updated and upgraded. Thanks to strong compatibility, it is common for different generations to coexist in the city. Liu Haopeng analyzed from the perspective of USB application market adoption, showing two trends: one is that in traditional applications, the pace of popularization of new standards varies; the other is emerging applications, where new standards play a driving role.

For example, gaming, VR/AR and other devices are the most conservative in adopting the new USB standard. Although they are in great demand, they are more eager for a unified interface, integrating all power cables, control cables, data cables, audio and video cables, etc. The new generation of USB standards such as USB4 meets the above requirements and is more suitable for this scenario. It can support 4K, 8K and even future 10K video transmission, plus advanced features such as low latency and variable refresh rate to bring users a better experience. , will speed up the adoption of the new USB standard for such applications.

He also mentioned that the development of the application market has prompted the evolution of USB interface technology to show the following trends: continue to challenge higher transmission speeds; continue to be compatible with multiple protocols, etc.

It is expected that around 2025, the transmission speed of the USB interface is expected to reach nearly 80Gbps, continuing to remain competitive with Thunderbolt. At the same time, Type-C, as a unified interface form, will further optimize its mechanical and electrical characteristics; and the connecting cables may all be replaced by active cables to meet the length requirements.

USB will also continue to maintain compatibility with multiple protocols, including USB standards of different generations, such as USB 3.1, USB 3.2 and USB4, as well as the fast charging standard USB PD, as well as DisplayPort, PCIe, Thunderbolt, and even HDMI and Ethernet in the future. Internet, etc. are likely to be included in the scope of USB interface support, becoming a veritable king of “domination of the world”.

Challenges and Response丨Xin Yaohui’s advanced USB IP solves the three challenges of high-speed interface design

There is considerable space in the USB market, but the rapid implementation and iteration of products have brought more challenges to chip design and testing: extremely high transmission speed, many interface protocols, many fast charging protocols, and accelerated protocol upgrades. As a high-speed interface IP supplier, Xinyaohui has the following insights and provides a flexible and easy-to-use complete solution based on years of design accumulation and excellent architecture of USB PHY IP.

Challenge 1: It needs to adapt to various complex application scenarios.

As shown in the figure, in order to support different encodings, including 8/10bit, 128/132bit, and optional 64/66bit; different protocols, USB, DP, and optional Thunderbolt, PCIe, etc., as well as a variety of transmission rates and Protocol electrical characteristics, etc. IP design needs to be considered comprehensively and optimized one by one.

Figure: USB PHY IP Design Challenges – Adapting to Complex Application Scenarios

Challenge 2: More stringent channel insertion loss budget.

The channel insertion loss of USB3.1 Gen1 5Gbps varies according to DFP and UFP, different interface types, different budgets, and different requirements for connecting cables. The USB3.1 Gen2 10Gbp unifies the budget of DFP and UFP, regardless of interface type and cable. But this actually increases the design requirements for packaging, PCB, and cables in disguise, and also increases the difficulty of PHY IP design. Because a chip must be adapted to a variety of different application scenarios, it puts forward higher requirements for IP design, whole chip system design and testing.

Figure: USB PHY IP Design Challenge – Tight Channel Insertion Loss Budget

Challenge 3: USB4’s complex transmitter and receiver equalization and strict bit error rate requirements.

USB4 link training adopts a feedback method similar to PCIe Training. While sending the training sequence, the transmitter sends back the FFE request from its receiver to the transmitter, and finds the optimal equilibrium value in the preset value. USB4 needs to support fast traversal of up to 16 presets. The receiving end should adapt to the cycle jitter of different frequencies. Each cycle jitter must pass the low bit error rate test of PRBS31. The protocol requires a bit error rate of 1e-12. Reduce the target bit error rate to 1e-13, or even lower.

Figure: USB4 PHY IP Design Challenges – USB4’s complex transmitter and receiver equalization and strict bit error rate requirements

Xinyaohui Advanced USB PHY IP Solution

In response to these design challenges, Xinyaohui provides flexible complete solutions to adapt to various application scenarios and is backward compatible, including USB4 and USB 3.1 Type-C solutions.

Xinyaohui USB 3.1 Type-C solution, with leading architecture and design, has been proven in a large number of mobile applications. For all applications requiring Type-C, USB speeds up to 10Gbps, DP HBR3 speeds up to 8.1Gbps, and features HDCP 2.3 content protection.

Xinyaohui USB4 IP solution supports all functions in the USB4 specification; via Type-C connection, supports USB4, DisplayPort, PCIe and Thunderbolt3; the new Router IP enables USB, PCIe and DisplayPort to transmit data streams while optimizing bandwidth; Up to 40Gbps (or 20Gbps) throughput for high-performance AI, high-speed storage, PC, notebook, mobile and tablet SoC designs.

Figure: Xinyaohui USB4 and USB 3.1 Type-C complete solution advantages

At the end of the speech, Liu Haopeng introduced to the guests that Xinyaohui Technology is a start-up IP company with an industry “dream team”, dedicated to enabling customers’ chip design and system applications through advanced semiconductor IP research and development services. The founding team of Xinyaohui Technology are top talents from IP design, chip design, software and other industries. They have worked with top and mainstream customers with mass production capabilities at home and abroad to create world-leading products, and have been iterating together for a long time, with more than 20 years of experience. Accumulation, well versed in the pain points of chip design, and can also provide a series of customized IP upgrade services. Xinyaohui Technology is willing to cooperate with a wider range of customers to help chip design manufacturers achieve greater success.