Now that the semiconductor process technology has progressed to 7nm, it will become more and more difficult to upgrade later. If you want to improve chip performance, you can also read the chapter on the context of wafer packaging.

This time, TSMC has introduced CoWoS (Chip on Wafer on Substrate) packaging technology, which puts logic chips and DRAM on a silicon interposer (interposer) and then packages them on a substrate. This is a 2.5D/3D packaging process, which can make the chip size smaller and have higher I/O bandwidth. However, because the cost is several times higher than that of ordinary packaging, there are not many customers currently using it.

On March 3, TSMC announced that it will jointly launch an enhanced CoWoS solution with Broadcom, which supports the industry’s first 2Xreticlesize interposer with an area of ​​about 1,700 square millimeters.

The new enhanced CoWoS platform can accommodate multiple logic system-on-chip (SoC), provides up to 96GB of HBM memory (six slices), and has a bandwidth of up to 2.7TB/s. Compared with the previous generation CoWoS, it has been improved by 2.7 times. If it is compared with PC memory, the increase is between 50 and 100 times.

TSMC said that this new-generation CoWoS platform can significantly increase computing power, support advanced high-performance computing systems with more SoCs, and is ready to support TSMC’s next-generation 5nm process technology.

Greg Dix, vice president of Broadcom’s Engineering for the ASIC Products Division, said, “I am delighted to work with TSMC to jointly refine the CoWoS platform and solve many design challenges on 7nm and beyond.

Author: Liuyun