[Introduction]In addition to performance, reliability and robustness are the most discussed topics for SiC MOSFETs. We define robustness as the ability of a device to withstand a specific special stress event, such as short circuit capability or pulse current handling capability. Reliability refers to the stability of the device under rated operating conditions over the target lifetime. Reliability-related phenomena include drift or destructive failure of certain electrical parameters. For hard failures, it is usually quantified in the form of the FIT rate. The FIT rate describes how many failures of a certain type of equipment are expected to occur in a certain period of time. At present, the cosmic ray effect mainly restricts the FIT rate of high-power silicon devices.

In the case of SiC, gate oxide reliability issues due to gate oxide electric field stress also need to be considered. As shown in the figure below, the total FIT rate of SiC is the sum of the cosmic ray FIT rate and the oxide FIT rate. For the cosmic ray failure rate, the FIT rate of a certain technology can be obtained experimentally. Based on these results and the application goals, a product design that meets the target FIT rate can be realized. Optimizing the electric field design of the drift region can often achieve low FIT rates. For the FIT rate of oxides, a screening process needs to be applied to reduce the FIT rate because the defect density of SiC is still quite high compared to silicon. However, even in our silicon power devices, gate oxide screening is still employed as a quality assurance measure.

The challenge for gate oxide reliability of SiC MOS devices is to guarantee a maximum failure rate below 1 FIT under given operating conditions for some industrial applications, which is comparable to today’s IGBT failure rates.

Since the quality and properties of silicon dioxide (SiO2) grown on silicon carbide and silicon materials are nearly identical, theoretically, Si MOSFETs and SiC MOSFETs of the same area and oxide thickness can withstand roughly the same amount of oxidation for the same amount of time. Layer electric field stress (same intrinsic lifetime). However, this only works if the device does not contain defect-related impurities, ie, extrinsic defects. Compared to Si MOSFETs, the extrinsic defect density in the gate oxide of SiC MOSFETs at this stage is much higher.

Electroscreening reduces reliability risks

Devices with extrinsic defects fail earlier than devices without defects. Defect-free devices can also fatigue failure, but have a long lifespan. Typically, the intrinsic failure time of a sufficiently thick defect-free oxide layer is orders of magnitude longer than that used in normal applications. Therefore, over a typical chip lifetime, the FIT rate of oxides is entirely determined by extrinsic defects.

The challenge of ensuring adequate gate oxide reliability for SiC MOSFETs is how to reduce the number of devices affected by extrinsic defects from a high percentage (eg 1%) at the end of the initial process to the time the product is shipped to Acceptable low ratio (eg 10ppm) for customers. One accepted way to achieve this is to use electroscreening.

During the electrical screening process, each device is in a gate-controlled stress mode. The stress mode is chosen in such a way that devices with severe defects will fail while devices without these defects, or devices with only non-critical defects, will pass the test. Devices that fail the screening will be removed from the production line. In this way, we convert potential reliability risks into yield losses.

In order for the device to withstand a certain gate stress, the gate oxide needs to have a specific minimum thickness. If the gate oxide thickness is too low, the device can experience intrinsic failure due to fatigue during screening, or a drop in threshold voltage and channel mobility after screening. On the other hand, a thicker gate oxide increases the threshold voltage and reduces the channel conductivity for a given VGS(on). The graph below illustrates the trade-off between gate oxide FIT rate and device performance, which is also discussed in .

We’ve put in a lot of time and samples to get a lot of data on the gate oxide reliability of SiC MOSFETs. As an example, we tested the on-state reliability at 150°C for 100 days on electrically screened SiC MOSFETs divided into three groups with different positive and negative gate stress biases applied to each group. Each set of samples has 1000 devices. The graphs below show the results under different gate oxidation process conditions, with significant improvements in process reliability for final mass production.

Using initial process conditions, less than 10 out of 1000 devices failed at twice the recommended gate bias of 30V. An improved implementation process reduces this number to just one fault at 30V and zero faults at 25V and -15V. The only failure is an extrinsic failure, however, this is not critical as failure will occur at a point well beyond the specified product lifetime under the rated gate bias service conditions.

Of course, in addition to evaluating the reliability of the on-state oxide, it is also important to evaluate the stress of the off-state oxide, because the electric field conditions in SiC power devices are closer to the limit of SiO2 than in silicon power MOS devices.

Shielding is a trade-off between on-resistance and reliability

The key strategy is to effectively shield the sensitive oxide regions through proper design of the deep p-well. The efficiency of shielding is a trade-off between on-resistance and reliability. In trench MOSFETs, the deep p-well forms a JFET-like structure beneath the channel region of the MOSFET, which can effectively facilitate shielding. This JFET (Junction Field Effect Transistor) adds an extra component to the on-resistance, mainly depending on the distance and doping between the buried p-regions. The design features of this shielding structure are critical to avoid gate oxide degradation or gate oxide breakdown during off-state.

To verify the off-state reliability of the CoolSiC™ MOSFETs, we stress tested over 5000 1200V SiC MOSFETs at 150°C, VGS=-5V and VDS=1000V for 100 days. These conditions are harsh enough for industrial applications. Limited by the breakdown voltage of the device, VDS cannot continue to increase.

Testing at higher drain voltages will distort the results as other failure mechanisms, such as cosmic ray induced failures, may occur. As a result, none of the tested devices failed during this off-state reliability test. Since the 650V device follows the same design criteria as the 1200V device, the same reliability is expected.

Source: Infineon

By Friedrichs Peter, Vice President SiC,

Infineon Technologies AG

Translated by: Zhao Jia