“Power management chips are widely used in board-level power systems, including controllers and power MOSFETs. However, for high-current power management chips, based on the technical characteristics of different semiconductor processes, that is, the difference in the processes required for the controller and MOSFET, it may not be possible to use the same semiconductor process to integrate the two on the same wafer (Wafer). Therefore, only a multiple-die structure can be used, which is called a multi-chip package (MCM) and a flip-chip package, resulting in an unsymmetrical pad outline.

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Author: Daniel Wang

Power management chips are widely used in board-level power systems, including controllers and power MOSFETs. However, for high-current power management chips, based on the technical characteristics of different semiconductor processes, that is, the difference in the processes required for the controller and MOSFET, it may not be possible to use the same semiconductor process to integrate the two on the same wafer (Wafer). Therefore, a multiple-die structure can only be used, which is called a multi-chip package (MCM) plus a flip-chip (Flip-chip) package, resulting in an unsymmetrical pad outline. If the SMA process cannot fully comply with the size requirements of the pads and stencils in the chip manual (some customers may have their own default CAD and SMA rules), the thickness of the solder may be insufficient or uneven. The pins of the chip mounted in this way are cracked or short-circuited due to the warpage of the board after long-term operation (corresponding to the board-level reliability test BLR, JESD22-A104), and the chip function is abnormal or even damaged. Therefore, it is of great significance to correctly understand and abide by the size rules of the pads and stencils of the chip, and make appropriate optimizations in advance, which is of great significance for improving the yield of the SMA process and the working life of the chip.

Chip pin size (footprint)

The chip data sheet will indicate the chip’s footprint (footprint), as shown in Figure 1 below. The pins of the chip are asymmetric in both the horizontal and vertical directions, and in the vertical direction, this situation is more obvious: the Pin25 AGND size is relatively large, while the PIN26-30 size is relatively small and scattered.Then due to the asymmetry of the left and right sides, if the thickness of the steel mesh and solder required for the product is not followed, it may lead to

• The thickness of the solder on the left and right sides is not uniform, and the thickness of the local solder is insufficient. In addition, the PCB, solder, PAD and chip have different thermal expansion coefficients, and the stress during temperature cycling will be different, which is easy to cause solder cracking.

• Due to the insufficient level of the chip position, the adjacent IO may be squeezed and flow to the adjacent IO due to uneven force on the solder, which may cause a short circuit.

Figure 1: Top view of the TPS542A52 chip (left) and pinout of the chip (right)

The land pattern and stencil size of the chip

The pad size of the chip on the PCB board is generally larger than the chip size in order to undertake the chip on the PCB board. Stencil (solder stencil) window, equal or slightly smaller than the pad.

Figure 2: TPS542A52 land pattern top view (left) and solder stencil top view (right)

Effects of different pad size and stencil thickness on solder thickness and uniformity (TPS542A52)

In practical applications, when CAD engineers of chip customers build CAD models for suppliers’ chips, they have a set of default CAD rules based on their own SMT process production line accuracy and experience, so they may not fully comply with the dimensions recommended in TI product manuals. . For most symmetrical packages such as QFP, BGA, LGA, etc., since the pads are symmetrical, the solder thickness is generally uniform even if it is not exactly the size of the pad stencil recommended by the supplier. But for non-standard packaged power chips, such as FLIP-CHIP QFN, because the power part occupies a large area, but only a few IO ports of VIN/SW/GND, while the control part has a small area but has many IO ports, so the tube The distribution design of the feet is prone to asymmetric pins. Therefore, different pad sizes and stencil sizes will reflect completely different lead welding quality and long-term reliability.

The following table Table 1 is the soldering quality (solder thickness and uniformity) of TPS542A52 under different pads and stencils and the pin profile after temperature cycle test.

Table 1

(1) The pad size is larger than TI
(2) Stencil opening size is smaller than TI
(3) TI recommends 125um stencil thickness

A The size of the pad is too large, the stencil is smaller and there are no two windows for PIN 25 (GND)

• Insufficient solder thickness, solder cracking

The overall amount of solder is insufficient, because the stencil opening is smaller than TI recommended and the pad size is too large, causing the solder under the pins to be spread out and flow to the external exposed pad. After the temperature cycle, the solder is prone to crack due to insufficient thickness, causing the chip pins to open and cause damage.

• Chip tilt

Since there are no multiple windows in PIN25, there are many voids in the PIN25 solder. As shown in Figure 3 below.

Figure 3 Solder void of PIN25 of GroupA Unit 1

B pad and stencil size both meet TI requirements, but the thickness of stencil is too thick and there are no two windows for PIN 25 (GND)

In order to solve the problem of insufficient solder thickness, some customers will directly increase the thickness of the stencil. The thickness of the solder is thick enough (>60um) to avoid the problem of solder crack. However, there is still a risk of short circuits due to the inclination of the weld in the horizontal direction. As shown in Figure 4 below.

• Solder is too thick

Still uneven, there is a risk of a short circuit with the solder bridge on the left.

Figure 4 Cross-sectional view of GroupB Unit 2

C pad and stencil dimensions and openings meet TI requirements, and stencil thickness also meets TI requirements

The thickness of the solder is uniform and greater than 60um, and the void of the solder under PIN25 is also small.

Figure 5 X-ray top view and section view of Group C Unit 4

Summarize

For chips with asymmetric footprint, it is recommended that customers design according to the pad and stencil size recommended by TI. The thickness of the chip solder is uneven, resulting in tilt and short circuit between the IOs. The thickness of the chip solder is insufficient, and it is easy to crack during the temperature cycle test.

For a larger single PIN pin, the more solder, the larger the void, and it is easy to cause imbalance. The opening can be appropriately divided into multiple small openings to reduce the actual amount of solder and reduce voids.

references

Texas Instruments, TPS542A52 4-V to 18-V Input, 15-A, Synchronous Buck Converter With Differential Remote Sense datasheet (Rev. C)

JESD22-A104 TEMPERATURE CYCLING | JEDEC