“Packaging is a really cool and interesting area by its very nature, and since I joined Intel, the ability to differentiate is stronger than ever.” – Johanna Swan, Research Director, Systems-in-Package, Intel Component Research Group

Intel CEO Pat Kissinger repeatedly referred to “Intel’s world-class packaging and assembly test technology” as he described how Intel made chips for customers through Intel Foundry Services (IFS) and differentiated itself. “We’ve seen a lot of interest in packaging technology from potential foundry customers,” Kissinger told investors last month.

Encapsulation has never been more popular.

But for Johanna Swan, the belated accolade is tied to her job. “We have to anticipate future needs and focus on what we believe will be valuable — but that’s more than five years into the future,” said Swan, director of packaging systems research at Intel’s Component Research Group.

An Intel Fellow, Swan, an expert in Electronic packaging technology, joined Intel in 2000 after 16 years at the Lawrence Livermore National Laboratory.

Swan and her team improved and developed new ways of packaging silicon chips—a result that not only attracted potential foundry customers, but also allowed Intel to offer a variety of leading-edge products. By definition, a package is an enclosure around one or more silicon dies that protects the dies from the outside world, dissipates heat, provides power, and connects them to the rest of the computer’s components.

“The package is there to make the external connections, but at the same time optimize the internal performance, all the way down to the transistor level,” Swan explained.

Researching on the fringes means “you need extraordinary persistence,” she adds. “Because it takes a long time to see results in a product, you have to be willing to tackle all kinds of interesting headaches and believe in the value of research in terms of its impact and the change it will create.”

To just call the changes in chip design and manufacturing caused by Intel’s packaging technology “small changes” is an understatement.

A new inflection point in the quest for Moore’s Law

“We’re currently moving from doing everything in a single way to creating products with multiple nodes, different silicon processes, and getting the most out of the application in each process node,” Swan explained.

She went on to add that the ability to assemble many individual silicon blocks together is “a really big inflection point…to effectively perpetuate Moore’s Law in a slightly different way than traditional.”

Swan explained that the traditional cornerstones of packaging, namely “performance,” “cost,” and “manufacturability,” will continue. But the introduction of new multi-dimensional advanced packaging technologies, such as Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and Foveros, gives chip designers “interesting knobs for optimizing and creating systems.”

An example of an application of this new approach is the upcoming XPU chip, Ponte Vecchio, which connects some 47 different silicon blocks in stacks, enabling new orders of magnitude performance for artificial intelligence and scientific computing.

“The Charm of Encapsulation”

Swan explained that the next cornerstone of packaging is what she calls “functional densification…that is, maximizing performance per unit volume.” Although packaging bears no resemblance to Moore’s Law, it has evolved to some extent through miniaturization, she said.

Swan points out that the relative size of the connections and wires (interconnects) in a package, compared to the size in a silicon wafer, “was often of a completely different order of magnitude in the past.” But as the capabilities of packaging technology shrink ( For example, the vertical interconnect pitch of die-to-die is well below 10 microns), “interfaces are converging between packaging and what Intel calls the last end of silicon.”

“Now all of a sudden, the wonderful thing about packaging is that it has the same feature size as the giant metal on the backside of the wafer,” Swan said.

“This shifts some of the burden of manufacturing into what is more factory-like today,” she added. But when you look at the total cost of a product, “we should be able to optimize it in a cost-reducing way.”

These complex products present a new set of challenges, Swan said, “but it’s really a good thing for Intel because we already have those advantages.”

For more than two decades, constant new challenges have kept Swan focused on next-generation packaging technologies. “I thought that packaging technology might only be interesting for a few years, but the fact that packaging involves many areas – including high-speed signaling, power delivery, as well as mechanical issues and material challenges. This shows that in packaging this topic , there are actually a lot of really interesting problems to solve.”

Create, pioneer and disrupt – thought provoking

She added: “The capabilities that can be created from this area are dazzling. If one is curious and wants to solve challenging problems, Intel is definitely the way to go. Packaging technology is on the rise.”

What’s next for Intel? Temporarily confidential. But Swan said that in addition to predicting changes in chip design and changes in customer needs, we will always pay attention to today’s technical bottlenecks and ways to improve.

“Then in other pioneering areas, you start to discover capabilities that haven’t really been discovered, and you can start thinking about how to do things in ways that other people haven’t thought of yet.”

“We’re committed to disruptive change,” Swan said. “At the heart of this art of change is making change without changing all the equipment, and it doesn’t require a whole new production line. Disruptive innovation is still achievable when done wisely. maximum effect.”

“In essence, packaging is a really cool and interesting area,” Swan added. “The ability to differentiate is stronger than ever since I joined Intel.”