Have you mastered the correct method of power sequence control?
“We often take for granted powering circuits on a printed circuit board, unaware that this can cause damage and a lossy or damageless latch-up condition. With the increasing number of System-on-Chip (SoC) ICs, the need for sequencing and management of power supplies also increases…
We often take for granted powering circuits on a printed circuit board, unaware that this can cause damage and a lossy or damageless latch-up condition. With the increasing number of System-on-Chip (SoC) ICs, the need for sequencing and management of power supplies also increases…
Although ADI’s data sheets usually provide enough information to guide you in designing the correct power-up sequence for each IC. However, some ICs explicitly require a proper power-up sequence to be defined. This requirement is fairly common in ICs that use multiple power supplies, such as converters (including ADCs and DACs), DSPs, audio/video, RF, and many other mixed-signal ICs.
Today we will discuss some of the more subtle power issues that design engineers must consider in new designs, especially when ICs require multiple different power supplies. Some of the more commonly used supply voltages today are: +1.8 V, +2.0 V, +2.5 V, +3.3 V, +5 V, −5 V, +12 V, and −12 V.
PULSAR ADC Example – Absolute Maximum Ratings
All ADI data sheets contain an “Absolute Maximum Ratings” (AMR) section, which describes the maximum voltage, current, or temperature that can be applied to a pin or device to avoid damage. The AD7654 PulSAR 16-bit ADC is an example of a mixed-signal ADC that uses three (or more) independent supplies. These ADCs require digital power (DVDD), analog power (AVDD), and digital input/output power (OVDD). They are ADCs and are used to convert analog signals into digital codes, so an analog core is required to handle incoming analog inputs. The digital core handles the bit-judgment process and control logic. The I/O core is used to set the levels of the digital outputs for interfacing with host logic (level shifting). The ADC’s power supply specifications can be found in the “Absolute Maximum Ratings” section of the corresponding data sheet. Table 1 is taken from the “Absolute Maximum Ratings” section of the AD7654 data sheet.
Table 1. Absolute Maximum Ratings for AD7654
Note that all three supplies in Table 1 range from −0.3 V to +7 V. The range of AVDD is +7 V to −7 V relative to DVDD and OVDD, which confirms that either AVDD or DVDD can be powered up first. In addition, it is also possible to power up either AVDD or OVDD first. However, there are limitations between DVDD and OVDD. The spec states that OVDD can only be up to 0.3 V higher than DVDD, so DVDD must be powered up before or at the same time as OVDD. If OVDD powers up first (assuming 5 V), DVDD powers up 5 V below OVDD, which does not meet the Absolute Maximum Ratings requirements and may damage the device.
The analog inputs INAx, INBx, REFx, INxN, and REFGND are restricted so that these inputs must not exceed AVDD + 0.3 V or AGND − 0.3 V. This means that if an analog signal or reference exists prior to AVDD, the analog core is likely to power up into a latched state. This is usually a lossless condition, but the current through AVDD can easily step up to 10 times the nominal current, causing the ADC to get quite hot. In this case, the internal electrostatic discharge (ESD) diode becomes forward biased, which in turn powers up the analog power supply. To solve this problem, the input and/or reference should be unpowered or unconnected when the ADC is powered up.
Likewise, the digital input voltage range is −0.3 V to DVDD + 0.3 V. This means that the digital input must be less than DVDD + 0.3 V. Therefore, at power-up, the DVDD must be powered up before or at the same time as the microprocessor/logic interface circuit. Similar to the analog core case above, the ESD diodes on these pins can also become forward biased, powering up the digital core to an unknown state.
Faster PulSAR ADCs, such as the AD7621, AD7622, AD7623, AD7641, and AD7643, are newer devices in this family and operate on a lower 2.5 V supply (the AD7654 uses a 5 V supply). The AD7621 and AD7623 have a well-defined power-up sequence. Table 2 is taken from the “Absolute Maximum Ratings” section of the AD7621 data sheet.
Table 2. Absolute Maximum Ratings for AD7621
Also, there are limitations between OVDD and DVDD. “Absolute Maximum Ratings” states: OVDD must be less than or equal to DVDD + 0.3 V, and DVDD must be less than 2.3 V. This limit no longer applies once DVDD reaches 2.3 V during power-up. If this limit is not followed, the AD7621 (and AD7623) may be damaged (see Figure 1).
Figure 1. Possible Power-Up/Shutdown Sequence—AD7621
Therefore, a typical power-up sequence might look like this: AVDD, DVDD, OVDD, VREF. However, every application is different and requires specific analysis. Note that device shutdown is just as important as device power-up, remember to follow the same specifications. Figure 1 shows a typical power-up/shutdown sequence for the AD7621.
For these ADCs, the analog input and reference are the same as described above. Applying voltage to any analog input pin can cause the ESD diodes to become forward biased, powering up the analog core to an unknown state.
The digital inputs and outputs of these ADCs are slightly different, as these devices should support 5 V digital inputs. These ADCs are speed upgrades to the AD7654, with digital inputs and outputs tied to the OVDD supply as it can support the higher 3.3 V voltage. Note: The digital input is limited to 5.5 V, while the AD7654 is DVDD + 0.3 V.
Example of a Sigma-Delta ADC
The AD7794 sigma-delta 24-bit ADC is another good example. Table 3 is taken from the “Absolute Maximum Ratings” section of the AD7794 data sheet.
Table 3. Absolute Maximum Ratings for AD7794
The problem with this ADC is related to the reference voltage, which must be less than AVDD + 0.3 V. Therefore, AVDD must be powered up before or at the same time as the reference voltage.
AD7794 Product Details:
Up to 23-bit effective resolution
Root Mean Square (RMS) Noise: 40 nV (at 4.17 Hz), 85 nV (at 16.7 Hz)
Power Consumption: 400 µA (typ)
Power save mode: 1 µA max
Low Noise Programmable Gain Instrumentation Amplifier
Bandgap Reference with 4 ppm/°C Typical Drift
Update rate: 4.17 Hz to 470 Hz
6 differential analog inputs
Internal clock oscillator
50 Hz/60 Hz simultaneous suppression
Reference voltage detection
Programmable Current Source
ADI offers many power sequencing devices. Generally speaking, its working principle is: when the output voltage of the first regulator reaches a preset threshold, a delay will begin for a period of time, and the subsequent regulators will not be enabled until the delay ends. The procedure during shutdown is similar. A sequencer can also be used to control the timing of logic signals such as power good signals, for example to apply a reset signal to a device or microprocessor, or simply to indicate that all power supplies are valid.
Most circuits requiring high speed and low power consumption today require multiple power supplies on PCBs, such as: +1.8 V, +2.0 V, +2.5 V, +3.3 V, +5 V, −5 V, +12 V, and − 12V. Powering these supplies on the PCB is not a trivial task. Careful analysis must be done to design a correct and reliable power-up and power-down sequence. Adopting discrete designs is becoming more and more difficult, and the solution is to use a power sequence control IC, which can change the power-on sequence by changing the code without changing the PCB layout.
The Links: LQ065T5AR05 NL6448BC3370G