“Director Li Changqi of the R&D Center of ASE Group recently shared the 2.5D/3D IC packaging technology of small chip integration at the Advanced Packaging Innovation Technology Forum of the World semiconductor Conference. Director Li said that the total amount of global data will reach 175ZB in 2025, and big data The timeliness of processing and transmission is increasingly important. System integration shortens the transmission distance and effectively improves the transmission rate and energy efficiency. With the development of silicon photonics (Silicon Photonics), the transmission bandwidth efficiency of light has become higher and higher, and the integration of light into packaging form is an important development trend in the future.

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Director Li Changqi of the R&D Center of ASE Group recently shared the 2.5D/3D IC packaging technology of small chip integration at the Advanced Packaging Innovation Technology Forum of the World semiconductor Conference. Director Li said that the total amount of global data will reach 175ZB in 2025, and big data The timeliness of processing and transmission is increasingly important. System integration shortens the transmission distance and effectively improves the transmission rate and energy efficiency. With the development of silicon photonics (Silicon Photonics), the transmission bandwidth efficiency of light has become higher and higher, and the integration of light into packaging form is an important development trend in the future.

Director Li also emphasized that system integration and SoC separation are the key factors driving the integration of advanced packaging and chiplets. In system integration, memory, power and optical integration are the main development opportunities. Split and SRAM split are the most important. In the chiplet integration technology, fine-pitch interconnection, large-scale integration, power transmission and heat dissipation are the main development directions in the future.

2.5D/3D IC Packaging Characteristics and Heterogeneous Integration

Heterogeneous integration needs to improve system performance through advanced packaging. Taking 2.5D/3D IC packaging as an example, it can provide high-density interconnection for memory and small chip integration, such as providing the line width and line spacing of Sub-micron, or five. The interconnection of layers is a good Interposer (intermediary layer). In addition, power integration can be completed through DTC Interposer and IPD/Si Cap technology, and high-performance long-distance data transmission can be provided through high-bandwidth non-package interconnection. ASE is currently working with partners to develop Optical Chiplet and Optical Interposer technologies to provide reliable solutions for further miniaturization.

Development Trend of Memory Integration

The demand for memory bandwidth is getting higher and higher, and the integration of high-bandwidth memory has become a key competitiveness. There are two main development trends of memory integration in the future. One is to integrate HBM3 to increase bandwidth, and the other is to do 3D integration and stacking, such as SRAM stacking and DRAM stacking. ASE took the lead in mass production of HBM1-integrated packages in 2015, HBM2 in 2017, and HBM2E in 2021, and is currently developing towards 3D integration.

Power Integration Si Cap Development Trend

As the power supply becomes higher and higher, the requirements for capacitor density also increase, so the importance of capacitor integration is particularly prominent. ASE is working with partners to develop different capacitance technologies, such as Trench Capacitor and Stacked Capacitor with higher capacitance density on Si Cap and DTC Interposer, to meet the increasing capacitance density need.

Optical Integration Development Trend

The issue of bandwidth and energy efficiency is the main bottleneck of long-distance transmission of electricity in the future, so optical integration has become one of the key development trends. At present, ASE and its partners are developing two different optical integration technologies. The first is the optical chiplet technology, which uses a 2.5D silicon interposer to integrate the optical chiplet and SoC technology to meet the highest energy efficiency and The highest bandwidth, such as for high-speed computational optical I/O requirements. Another development trend is the optical interposer technology based on 3D integration, that is, the Electronic IC is on the top and the photonic IC is on the bottom. This integration method can provide higher bandwidth-level energy efficiency requirements and can be applied to networks. switch.

ASE continues to develop different advanced packages such as FOCoS with Fan Out package, 2.5D/3D IC package, Hybrid Bonding technology, etc., and cooperates with industry chain partners to meet the requirements of system integration and small chip Chiplet integration development requirements.