[Guide]Most MOSFETs in power applications are surface mount devices (SMD), including packages such as SO8FL, u8FL, and LFPAK. These SMDs are often chosen for their good power capabilities, while being small in size, which facilitates a more compact solution. Although these devices have good power capabilities, sometimes the heat dissipation is not ideal.

Since the leadframe of the device (including the exposed drain pad) is soldered directly to the copper area, this causes heat to travel primarily through the PCB. The rest of the device is enclosed in the plastic encapsulant and can only dissipate heat through air convection. Therefore, the heat transfer efficiency depends largely on the characteristics of the circuit board: the area size, number of layers, thickness and layout of the copper clad. This happens regardless of whether the board is mounted to the heatsink or not. Usually the maximum power capability of the device is not optimal because the PCB generally does not have high thermal conductivity and thermal mass. To solve this problem and further reduce the size of the application, a new MOSFET package has been developed in which the lead frame (drain) of the MOSFET is exposed on the top of the package (as shown in Figure 1 for example).

Figure 1. Top thermal package

Layout advantage of top cooling

While traditional power SMDs are good for miniaturized solutions, they require that no other components be placed below them on the back of the board due to thermal considerations. Some space on the board could not be used, resulting in a larger overall size of the final board. Top-cooled devices can get around this problem: the heat is dissipated through the top of the device. In this way, the board position under the MOSFET can be used to place components.

This space can be used to arrange the following components (but not limited to):

● Power devices

● Gate drive circuit

● Supporting components (capacitors, buffers, etc.)

This, in turn, reduces board size and reduces paths for gate drive signals, resulting in a more ideal solution.

Figure 2. PCB component space

In addition to providing more layout space, top-cooled devices also reduce thermal overlap compared to standard SMD devices. Most of the heat dissipation from the top cooling package goes directly into the heat sink, so the PCB experiences less heat. Helps reduce the operating temperature of surrounding devices.

Thermal Performance Benefits of Top Cooling

Unlike traditional surface-mount MOSFETs, the top-cooled package allows the heat sink to be attached directly to the device’s lead frame. Since metals have high thermal conductivity, heat sink materials are usually metals. For example most heat sinks are made of aluminum and have a thermal conductivity between 100-210 W/mk. This way of dissipating heat through high thermal conductivity materials greatly reduces thermal resistance compared to the conventional way of dissipating heat through the PCB. Thermal conductivity and material size are key factors in determining thermal resistance. The lower the thermal resistance, the better the thermal response.

Rθ = absolute thermal resistance

Δx = thickness of material parallel to heat flow

A = cross-sectional area perpendicular to heat flow

k = thermal conductivity

In addition to improving thermal conductivity, heat sinks also provide greater thermal mass – which helps avoid saturation, or provides a larger thermal time constant. This is because the dimensions of the top-mounted radiator can vary. Thermal mass or heat capacity is proportional to a given temperature change for a given amount of thermal energy input.

Cth = heat capacity, J/K

Q = thermal energy, J

ΔT = temperature change, K

PCBs tend to have different layouts and lower copper thickness, resulting in lower thermal mass (heat capacity) and poor heat spread. All of these factors make standard surface mount MOSFETs less than optimal thermal response when used. In theory, a top-cooled package has the advantage of dissipating heat directly from a high thermal mass, high thermal conductivity source, so its thermal response (Zth (C°/W)) will be better. In the case of a certain junction temperature rise, better thermal response will support higher power input. Thus, for the same MOSFET chip, a chip in a top-cooled package will have higher current and power capabilities than a chip in a standard SMD package.

Figure 3. Thermal path for top-cooled package (top) and SO8FL package (bottom)

Test Setup for Thermal Performance Comparison

To demonstrate and validate the thermal performance benefits of top cooling, tests were performed comparing the die temperature rise and thermal response of TCPAK57 and SO8FL devices under the same thermal boundary conditions. For a valid comparison, both devices were tested under the same electrical conditions and thermal boundaries. The difference is that the heatsink for the TCPAK57 is mounted above the device, while the heatsink for the SO8FL device is mounted on the bottom of the PCB, directly below the MOSFET area (Figure 3). This is a reproduction of how the device is used in a field application. Different thicknesses of thermal interface material (TIM) were also used during testing to verify which device packages could be optimized with different thermal boundaries. The overall test works as follows: Apply a fixed current (and therefore constant power) to both devices and monitor the change in junction temperature to see which device performs better.

Figure 4. Application Setup for Each Device

Component Selection and PCB Layout

In terms of device selection, the MOSFETs in each package have the same die size and use the same technology. This is to ensure that each device has the same power dissipation for a given current and to make the thermal response consistent at the package level. This way, we can be confident that the measured thermal response differences are due to package differences. For these reasons, we chose to use TCPAK57 and SO8FL. They come in slightly different clip and leadframe designs, one leaded (TCPAK57) and one leadless (SO8FL). It should be noted that these differences are small and do not have a large impact on the steady-state thermal response, so they can be ignored. After the parameters are given, the selected devices are as follows:

● NVMFS5C410N SO8FL

● NVMJST0D9N04CTXG TCPAK57

To further ensure that all other thermal boundaries remain equivalent, we designed two identical PCBs to house either the SO8FL package or the TCPAK57 package. The PCB is designed as a 4-layer board with 1 oz copper per layer. The dimensions are 122mm x 87mm. The SO8FL board does not have thermal vias connecting the drain pad to other conductive layers of the board (which is not optimal for heat dissipation); it can be used as the worst case case for heat dissipation in this comparison setup.

Figure 5. Each layer of the PCB

(Layer 1 is shown on the upper left, Layer 2 is shown on the upper right,

Layer 3 is shown on the lower left, and layer 4 is shown on the lower right)

Heat spreaders and thermal interface materials (TIMs)

The heatsink used in the tests was aluminum and specifically designed to be mounted to the PCB. The 107mm x 144mm heatsink is liquid cooled with a 35mm x 38mm cooling area directly under the MOSFET locations. The liquid that passes through the radiator is water. Water is the commonly used coolant in field applications. For all test scenarios, the flow rate was set to a fixed value of 0.5 gpm. The water provides additional thermal capacity, transferring heat from the heat sink to the water supply and helping to cool the device.

Figure 6. Application settings

To better facilitate heat dissipation across the MOSFET interface, a thermal gap filler should be used. This helps to fill in possible imperfections in the interface surface. Air is a poor conductor of heat, and any air gap increases thermal resistance. The TIM used in the tests was Bergquist 4500CVO caulk, which has a thermal conductivity of 4.5 W/mK. Several different thicknesses of this TIM were used to demonstrate the possibility of thermal response optimization. The fixed thickness is achieved by precision spacers used between the circuit board and heatsink. The target thickness used was:

● ~200 µm

● ~700 µm

Test circuit and heating/measurement method

The chosen on-board circuit configuration is a half-bridge setup as it represents a common field application. The proximity of the two devices to each other also accurately reflects the field layout, as shorter traces help reduce parasitics. This plays a role in the thermal response due to the thermal overlap between the devices.

To enable associated heating at lower current values, the current is passed through the body diode of the MOSFET. To ensure this is always the case, short the gate to source pins. The thermal response of a given device is obtained by heating the half-bridge FETs until a steady-state junction temperature (no rise in temperature), then monitoring the source with a small 10 mA signal source as the junction temperature returns to the cool-state temperature Drain voltage (Vsd). The time required to reach thermal steady state during heating is equal to the time to return to the de-energized state. The Vsd of the body diode is linear with the junction temperature, so it can be related to ΔTj using a constant (mV/C°) ratio (determined by characterization of each device). The ΔTj for the entire cooling period is then divided by the power dissipation at the end of the heating phase to obtain the thermal response (Zth) for a given system.

The 2 A supply, the 10 mA supply and the measurement of Vsd are all handled by the T3ster. The T3ster is a commercially available test device designed to monitor thermal response. It calculates the thermal response using the method mentioned earlier.

Figure 7. Circuit Diagram

Thermal comparison results

The thermal response results for each device were measured under two conditions:

● 200 μm TIM

● 700 μm TIM

The purpose of these two measurements is to determine which package has a better thermal response in a given system under control, and which device’s thermal response can be optimized by external cooling methods. It is important to note that these results are not applicable to all applications but are specific to the mentioned thermal boundary.

Package comparison using 200 μm TIM mounted to heat sink

For the first test run, each device was mounted on a water-cooled heat sink using a 200 μm TIM. Each device receives a 2 A pulse until steady state. T3ster monitors Vsd during cooling and correlates it back to the system’s thermal response curve. The steady-state thermal response value of the top cooling is ~4.13 C°/W, while that of SO8FL is ~25.27 C°/W. This large difference is in line with expected results, since the top thermal package is mounted directly to a high thermal conductivity, large thermal capacity heat sink for good heat spread. For SO8FL, due to the poor thermal conductivity of the PCB, the thermal conductivity is poor.

To help understand how to take advantage of these advantages in an application, thermal response values ​​can be related to the amount of power each device can handle. The power required to increase Tj from a coolant temperature of 23 C° to a maximum operating temperature of 175 C° is calculated as follows:

NOTE: This power difference is to be expected in this particular thermal system.

In this thermal system, the top cooling unit can handle 6 times the amount of power than the SO8FL. In field applications, this can be exploited in several different ways. Here are some of its advantages:

● When the required current is constant, a smaller heatsink can be used compared to SO8FL due to the increased power capability. Thereby possible cost savings.

● For switch-mode power supply applications, the switching frequency can be increased while maintaining a similar thermal margin.

● Can be used in higher power applications not originally suitable for SO8FL.

● When the chip size is constant, the top cooling device will have a higher safety margin than SO8FL, and the operating temperature will be lower under a given current demand.

Figure 8. Thermal response curve using 200 μm TIM

Figure 9. Temperature profile using 200 μm TIM

Package comparison using 700 μm TIM mounted to heat sink

Another test run was performed with a TIM thickness of 700 μm. This is to compare the change in thermal response with the 200 μm TIM test to verify the effect of the external cooling method on each package. This test operation yielded the following thermal response results: 6.51 C°/W for the top heat sink and 25.57 C°/W for the SO8FL. For top cooling, the difference between the two TIM operations is 2.38 C°/W, while the difference for SO8FL is 0.3 C°/W. This means that this external heat dissipation method has a large impact on the top cooling device and little impact on the SO8FL. This is also expected since the thermal response of the top cooling device is dominated by the thermal resistance of the TIM layer. TIMs have low thermal conductivity compared to heat sinks. Therefore, as the thickness increases, the thermal resistance increases, resulting in a higher Rth.

SO8FL TIM changes happen between the board and the heatsink. Its device heat must travel through the board to reach the TIM and heat sink, so thickness variations have little effect on the thermal resistance of the primary heat path. Therefore, the variation in thermal response is small.

These variations in thermal response due to variations in TIM thickness demonstrate the overall advantage of top-cooled packaging. The TCPAK57 has an exposed lead frame on top of the package, allowing better control of the thermal resistance of the heat path. This feature can be exploited to optimize thermal response for specific applications and cooling methods. This in turn provides a more controllable and beneficial power capability. Depending on the PCB characteristics, SO8FL and similar SMD devices are difficult to dissipate heat through the board on which they are placed. This is a non-controllable factor because there are many other variables in PCB design to consider besides heat dissipation.

Figure 10. Temperature profile using a 700 μm TIM

Figure 11. Temperature profile using a 700 μm TIM

Summary

The top-cooled package avoids heat dissipation through the PCB, shortening the heat path from the chip to the heat sink, thereby reducing the thermal resistance of the device. Thermal resistance is directly related to heat sink and thermal interface material properties. Low thermal resistance can bring many application advantages, such as:

● For a certain amount of current required, a smaller top cooling device can be used compared to standard SMD due to the increased power capability. In turn, this could lead to cost savings.

● For switch-mode power supply applications, the switching frequency can be increased while maintaining a similar thermal margin.

● Can be used in higher power applications where standard SMDs would otherwise not be suitable.

● When the chip size is constant, the top cooling device will have a higher safety margin than the equivalent SMD device, and the operating temperature will be lower under the given current demand.

Stronger thermal response optimization capabilities. This is accomplished by varying the thermal interface material and/or thickness. The thinner and/or better thermal conductivity the TIM, the lower the thermal response. Thermal response can also be changed by changing heat sink characteristics.

Top-cooled packaging reduces heat spread through the PCB, which in turn reduces thermal overlap between devices.

The top heat dissipation makes it unnecessary to connect the heat sink to the back of the PCB, so the components on the PCB can be arranged more compactly.