DRAM fault identification due to leakage current and parasitic capacitance
“Since the 20nm technology node, leakage current has been the leading cause of device failure in dynamic random access memory (DRAM) designs. Problems caused by leakage currents in DRAM designs can lead to reduced reliability even if the underlying device does not exhibit significant structural anomalies. Leakage current has become a critical consideration in DRAM device design.
Since the 20nm technology node, leakage current has been the leading cause of device failure in dynamic random access memory (DRAM) designs. Problems caused by leakage currents in DRAM designs can lead to reduced reliability even if the underlying device does not exhibit significant structural anomalies. Leakage current has become a critical consideration in DRAM device design.
Figure 1. (a) DRAM memory cell; (b) gate-induced drain leakage current (GIDL) in cell transistors; (c) dielectric leakage between bit line contact (BLC) and storage node contact (SNC); ( d) Dielectric leakage at DRAM capacitors.
DRAM memory cells (Figure 1(a)) lose stored data when the power is turned off, so they must be constantly refreshed. The amount of time a memory cell can store data before data loss, that is, retention time, is a key feature of DRAM, and the retention time is limited by leakage current.
There are two important leakage mechanisms that affect the data retention time of DRAM. The first is cell transistor leakage. Cell transistor leakage in DRAM is mainly due to gate-induced drain leakage current (GIDL) (Figure 1(b)), which is the leakage current caused by the high electric field effect at the drain junction. Under negative gate bias, the gate generates a depletion region (N+ drain region), which in turn generates an enhanced electric field in the region, and the band bending caused by this electric field results in band-to-band tunneling ( BTBT). At this time, electrons and minority carriers moving at the gate can tunnel into the drain, causing unnecessary leakage current.
The second leakage mechanism in DRAM is dielectric leakage between the bit line contact (BLC) and the storage node contact (SNC) (Figure 1(c)). Dielectric leakage typically occurs inside capacitors, where electrons flow through the metallic and dielectric regions (Figure 1(d)). Dielectric leakage occurs when electrons tunnel from one electrode to another through the dielectric layer. As the process node shrinks, the distance between BLC and SNC is gradually shortening, so this problem is becoming more and more serious. Manufacturing process variations of these structural elements can also negatively affect dielectric leakage between bit line contacts and storage node contacts.
Virtual Manufacturing Platform SEMulator3D®The design and process flow data can be used to build a 3D model of the DRAM device. After completing the “virtual” fabrication of the device, the user can view the leakage path from any direction through the SEMulator3D viewer, and can calculate the total leakage value. This feature can go a long way in understanding the impact of process variations on DRAM leakage current. The drift/diffusion solver in SEMulator3D provides current-voltage (IV) analysis, including GIDL and junction leakage calculations, for co-optimization of integrated design techniques. Users can also view changes in leakage values by changing the design structure, doping concentration, and bias strength.
Figure 2. (a) Variations of gate voltage and drain current at different drain voltages; (b) Variations of gate voltage and drain current at different gate oxide thicknesses (+/-1nm) Curve.
Figure 2 shows that GIDL increases with gate oxide thickness. The thinner the gate oxide, the higher the potential between the gate and drain of the modeled device.
Figure 3. (a) and (b) Leakage current between BLC and SNC in structures with and without BLC residue; (c) Variation of total leakage current under voltage sweep.
Figure 3 shows the dielectric leakage path in SEMulator3D and the total current difference between the bitline contact and the storage node contact, highlighting the effect of manufacturing variation of the BLC during the etch process. As shown in Fig. 3(c), due to the influence of process variation, the total leakage current of the structure with BLC residue is higher than that of the structure without BLC residue.
Figure 4. (a) DRAM capacitor Z-plane cross-sectional image and dielectric leakage path; (b) capacitor X-plane interface image and dielectric leakage path; (c) total leakage current versus bias intensity.
Figure 4 shows an example of dielectric leakage from a DRAM capacitor. Figures 4(a) and 4(b) are the Z-plane and X-plane cross-sectional views of the DRAM, respectively, and the projections of the dielectric leakage paths on these two planes as observed in the SEMulator3D device model. Figure 4(c) shows the leakage current at the bottom layer (BTM) electrode as a function of applied bias.
Figure 5. (a) Doping concentration view of a DRAM cell showing the type (and expected location) of capacitance at wordline WL2 and other nodes when an AC signal is applied to wordline WL2; (b) wordline WL2 and device Calculate the capacitance between other nodes on the
Another important factor affecting DRAM performance is the parasitic capacitance of the device. Alternating current (AC) analysis should be performed during DRAM development because bit line coupling can cause write recovery time (tWR) delays and other performance glitches. Since doped polysilicon is used not only for transistor gates, but also for bit line contacts and storage node contacts, which leads to several potential parasitic capacitances (see Figure 5(a)), capacitance measurements must be performed on the entire device . SEMulator3D has built-in AC analysis capabilities to measure parasitic capacitance values of complex simulated 3D structures. For example, by simulating the application of a small AC signal to word line WL2, SEMulator3D can obtain the capacitance values between word line WL2 and all other nodes in a newly designed DRAM structure, as well as their curves as a function of voltage (Figure 5 (b). )).
All in all, leakage current and parasitic capacitance from various sources can cause DRAM failure. During DRAM development, engineers need to carefully evaluate these failure modes, and of course the impact of process variations on leakage currents and parasitic capacitances. Next-generation routing for DRAM can be simplified by “virtually” building 3D devices using anticipated process flows and process variations, and then analyzing parasitic and transistor effects under different process conditions. SEMulator3D integrates 3D process models, R/C analysis and device analysis functions to quickly verify whether DRAM device structures are prone to leakage current or parasitic capacitance failures under different process assumptions.
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